1. Field of the Invention
The invention relates to a method of manufacturing integrated circuits (ICs), and more particularly to a method of manufacturing interconnects.
2. Description of the Related Art
Due to the further high integrity of ICs, chips cannot provide sufficient areas for interconnections manufacturing at all. Therefore, to cooperate with the increased requirements for interconnects manufacturing after the miniaturization of MOS transistors, it is necessary for IC manufacturing to increasingly adopt a design with more than two metal layers. In particular, a number of function-complicated products, such as microprocessors, even require 4 or 5 metal layers to complete the internal connections thereof. Generally, an inter-metal dielectric (IMD) layer is used to electrically isolate two adjacent metal layers from each other. Moreover, a conductive layer used to electrically connect the two adjacent metal layers is called a via plug in semiconductor industry.
In a prior method for manufacturing a via plug in a multilevel interconnect process, a dielectric layer is first formed on a metal layer. Then, a patterned photoresist is formed on the dielectric layer. A via hole is formed in the dielectric layer by etching. Next, a conductive layer, such as a tungsten layer, is deposited in the via hole, wherein the conductive layer is a so-called via plug. Repeat the above-stated steps to completely implement a multilevel interconnects process.
However, during etching for forming the via hole, the corresponding part of the lower metal layer cannot be completely exposed through the via hole owing to poor etching. As a result, the contact resistance between the subsequently formed via plug and the lower metal is increased because of the reduced contact area therebetween after the via plug is formed. When the poor etching becomes more serious, it may even cause that the via plug is thoroughly disconnected from the lower metal layer, leading to an open circuit.
FIGS. 1A-1B shows a method of manufacturing traditional interconnects.
Referring to FIG. 1A, a substrate 100 with a planarized surface is first provided, wherein devices already formed in the substrate 100 is not shown. A conductive layer (not shown) located on the substrate 100 is patterned to form a conductive line 102. Moreover, the conductive line 102 is electrically connected to a conductive region (not show) in the substrate.
Thereafter, a dielectric layer 104, such as a silicon oxide layer, is formed over the substrate 100 by chemical vapor deposition (CVD). Planarization is performed on the dielectric layer 104 by chemical mechanical polishing until the height of the dielectric layer 104 is approximately equal to that of a subsequently formed vial hole, thereby forming a dielectric layer 104a.
Referring to FIG. 1B, a via hole 106 is formed in the dielectric layer 104a by traditional photolithography and etching. A glue/barrier layer (not shown) is formed along the surfaces of the dielectric layer 104a and the via hole 106 thereby to improve its adhesion to a subsequently formed conductive layer. Then, a conductive layer (not shown), such as a tungsten layer, is formed on the dielectric layer and completely fills the via hole 106 by chemical vapor deposition. Finally, part of the conductive layer over the surface of the dielectric layer 104a is removed by etch back or chemical mechanical polishing thereby to form a via plug 108.
However, the contact area between the conductive line 102 and the via plug 108 is greatly decreased owing to a serious poor etching. It may even cause that the via plug 108 is completely disconnected from the conductive line 102, leading to an opening circuit 110.